Memory cells have traditionally been used to store bits of data. It is also possible to architect a memory cell so that the memory cell is able to perform some simple logical functions when multiple memory cells are connected to the same read bit line. For example, when memory cells A, B, and C are connected to a particular read bit line and are read simultaneously, and the memory cells and read bit line circuitry are designed to produce a logical AND result, then the result that appears on the read bit line is AND (a, b, c) (i.e. “a AND b AND c”), where a, b, and c represent the binary data values stored in memory cells A, B, and C respectively. More particularly, in these computational memory cells, the read bit line is pre-charged to a logic “1” before each read operation, and the activation of one or more read enable signals to one or more memory cells discharges the read bit line to a logic “0” if the data stored in any one or more of those memory cells=“0”; otherwise, the read bit line remains a logic “1” (i.e. in its pre-charge state). In this way, the read bit line result is the logical AND of the data stored in those memory cells.
Some computational algorithms (e.g. searches) are performed such that, as the algorithm proceeds, various portions of the computational memory cell array are identified as containing data that is irrelevant to the final result. Since pre-charging the read bit line in a portion of the computational memory cell array consumes power, it is desirable to be able to temporarily inhibit the pre-charge in these “irrelevant” portions of the computational memory cell array, from the time they are identified as such until the algorithm completes, to save power during that time. It is also desirable to be able to inhibit writes to the memory cells in such “irrelevant” portions of the computational memory cell array, for the same reason.
Furthermore, it is also desirable to be able to inhibit writes to the memory cells in selective portions of the computational memory cell array on a per-write-operation basis, not to save power, but rather to enhance the computational capability of the computational memory cell array.